分类： 活动

SEOUL, South Korea and CUPERTINO, Calif., March 26, 2012 – MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, today, announced that it will host its 2012 foundry technology symposium in Hsinchu, Taiwan, on Friday, April 13th.

The 2012 foundry symposium will provide participants with an in-depth understanding of MagnaChip’s manufacturing services (foundry) business, its distinct specialty manufacturing processes, technology roadmap as well as current and future semiconductor and foundry trends.

MagnaChip will provide an in-depth overview of its specialty process technologies and will highlight its technology portfolio and roadmap to include such applications as mixed-signal, power and high voltage CMOS as well as non-volatile memory targeted at smartphones, tablet PCs and Ultrabooks. MagnaChip will also feature its value-added, on-line customer services tool known as “iFoundry” at the symposium.

The keynote speaker for this event, from IHS iSuppli, will deliver an update on semiconductor and foundry market trends. More than one hundred fabless and other semiconductor companies are expected to attend MagnaChip’s 2012 Technology Symposium.

Attendance is open to all interested semiconductor and design house participants. To sign up for the foundry technology symposium and for more details, please contact Stanley Park of MagnaChip Semiconductor at stanley.park@magnachip.com.

CONTACTS:

In the United States:

Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:

Chankeun Park
Senior Manager, Public Relations
Tel.+82-2-6903-3195
chankeun.park@magnachip.com

SEOUL, South Korea and CUPERTINO, Calif., March 12, 2012 — MagnaChip Semiconductor Corporation (“MagnaChip Semiconductor”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, announced today that it now offers a 0.13um triple gate oxide CMOS process that will support wide voltage ranges for mobile device applications.

This 0.13um triple gate oxide CMOS process features one additional layer of gate oxide introducing 1.8V CMOS into a standard 1.2/3.3V CMOS array on 0.13um technology. This process is fully compatible with the standard CMOS process and is designed to keep all device parameters unchanged within process variation ranges.

Using a modular characteristic for IC design provides added flexibility by allowing the selection of either 1.2/3.3V or 1.2/1.8/3.3V CMOS processes without the need for design reverification. The triple gate oxide process for 1.2/1.8/3.3V also allows for a reduction in chip size providing a more cost-effective manufacturing process through optimization and integration of various functional blocks into one compact chip. This is particularly useful for mobile device applications.

“We are very pleased to offer a 0.13um triple gate oxide CMOS process solution for wide voltage, mixed-signal applications,” said T.J. Lee, Executive Vice President and General Manager of MagnaChip’s Corporate Engineering. “This is an example of our dedication and effort to expand our technology to premium mixed-signal processes at advanced technology nodes. Our goal is to continue to provide differentiated process solutions to meet the application-specific needs of our worldwide foundry customers.”

About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip Semiconductor believes it has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, large portfolio of registered and pending patents and extensive engineering and manufacturing process expertise. For more information, please visit www.magnachip.com.

CONTACTS:

Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:

Chankeun Park
Senior Manager, Public Relations
Tel.+82-2-6903-3195
chankeun.park@magnachip.com

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, today announced that MagnaChip’s foundry services has begun ramping its 0.35um mixed-signal process for MEMS (Micro Electro Mechanical Systems) Accelerometer applications.

The MEMS Accelerometer is a device which measures gravity and the acceleration of materials. One of the major features of a MEMS device is its ability to instantly detect motion change and impact. MEMS devices are now widely found in mobile applications such as handsets, personal navigation devices as well as game console controllers.

MagnaChip’s low noise and very cost effective 0.35um mixed-signal technology has allowed us to successfully ramp to production the MEMS Accelerometer applications used in mobile devices. These products will benefit from our premium mixed-signal process to ensure their accuracy and functionality.

“We are pleased to announce the availability of our 0.35um mixed-signal foundry process for MEMS Accelerometer applications used in mobile devices,” said Namkyu Park, Vice President of MagnaChip’s Foundry Marketing. “This is an example of our continued effort to develop highly differentiated mixed-signal technology solutions that meet the growing application-specific needs of our foundry customers.”

About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip believes it has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, a large portfolio of registered and pending patents and extensive engineering and manufacturing process expertise. For more information, please visit www.magnachip.com.

CONTACTS:

In the United States:

Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:

Chankeun Park
Senior Manager, Public Relations
Tel.+82-2-6903-3195
chankeun.park@magnachip.com

SEOUL, South Korea and CUPERTINO, Calif., Dec. 12, 2011 – MagnaChip Semiconductor Corporation (“MagnaChip Semiconductor”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, today announced that it now offers a redistribution layer (RDL) metal process for wafer bumping and an IO structure and process that is fully compatible with copper wire bonding. This process is designed to reduce semiconductor packaging costs while meeting the specialized application needs of foundry customers.

The redistribution layer metal process converts wire bond pads at the perimeter of the die to an array of bump pads that are relocated to the center area of the die. The relocation of pads allows for a larger pad pitch for wafer bumping making it possible to use low cost solder bumps instead of plated bumps. The redistributed bond pad process has recently found its way into other advanced packaging methodologies such as wafer-level chip-scale packaging, system-in-package, and 3-D packaging. This process requires one additional aluminum layer and is fully compatible with MagnaChip’s standard CMOS process.

Related to packaging trends, copper versus gold wire bonding has become one of the preferred methods for semiconductor interconnection because of its cost and performance features. Copper is a lower cost alternative to gold for packaging applications and has higher electrical and thermal conductivity making copper wire an excellent bonding material. In addition, copper bonds have greater reliability at elevated temperatures than gold bonds because of its lower tendency to form intermetallic compounds. One of the major challenges of copper wire bonding had been the significant mechanical stress imposed on bonding pads. This stress often resulted in dielectric cracks beneath the pads. MagnaChip resolved this issue in cooperation with the major packaging companies, including Amkor.

T.J. Lee, Senior Vice President and General Manager of MagnaChip’s Corporate Engineering stated, “We are very pleased to announce the offering of cost competitive backend processes such as the redistribution layer metal process and copper wire bonding. Our goal is to continue to develop highly differentiated and cost-effective technology solutions to meet the increasing application specific needs of our foundry customers.”

About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip Semiconductor has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, a large portfolio of registered and pending patents, and extensive engineering and manufacturing process expertise. For more information, please visit www.magnachip.com.

CONTACTS:

In the United States:
Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:
Chankeun Park
Senior Manager, Public Relations
Tel. +82-2-6903-3195
chankeun.park@magnachip.com

SEOUL, South Korea, Nov. 7, 2011 — MagnaChip Semiconductor Corporation (“MagnaChip Semiconductor”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, today announced that it now offers cost competitive compact standard cell libraries targeting low power applications in 0.18um and 0.35um technologies.

The new standard cell library features a smaller cell area and lower operating power by incorporating a compact design architecture. The cell area is reduced by up to 25% and the operating power consumption by a maximum of 60% compared with the use of conventional design libraries. In addition, these new compact standard cell libraries have the advantage of increased speed in addition to leakage and latch up control when compared to previous compact standard cell libraries. Any weakness to latch up is sharply reduced by using a self-well bias contact scheme.

T.J. Lee, Senior Vice President and General Manager of MagnaChip’s Corporate and SMS Engineering commented, “We are very pleased to announce the offering of our competitive compact standard cell library for cost effective and low power applications These cell libraries will provide cost competitiveness and design flexibility to meet the increasing application specific needs of our foundry customers.”

About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip Semiconductor has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, a large portfolio of registered and pending patents, and extensive engineering and manufacturing process expertise. For more information, please visit www.magnachip.com.

CONTACTS:

In the United States:

Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:

Chankeun Park
Senior Manager, Public Relations
Tel.+82-2-6903-3195
chankeun.park@magnachip.com

SEOUL, South Korea, Sept. 12, 2011 – MagnaChip Semiconductor Corporation (“MagnaChip Semiconductor”) (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, today announced that it will offer high density metal-insulator-metal capacitor and deep trench capacitor processes for integration into MagnaChip’s standard CMOS mixed signal process.

The high density metal-insulator-metal capacitor process provides capacitance values of 4, 6, 8, and 10fF/um(2). This process replaces the industry standard silicon nitride insulator layer with a high dielectric constant material layer in order to achieve high capacitance per unit area while suppressing leakage current. This high density capacitor can substantially reduce die area in applications that need high total capacitance for the purpose of charge storage and noise decoupling.

The deep trench capacitor consists of an array of small deep trenches constructed into the silicon substrate. This 3-D capacitor has high capacitance of 22 fF/um(2) and breakdown voltage of 25V. This process is specifically optimized to make series resistance low enough for fast switching applications and will be released for production in December 2011.

TJ Lee, Senior Vice President and General Manager of MagnaChip’s Corporate and SMS Engineering stated, “We are very pleased to announce the offering of our specialty capacitor processes such as high density MIM capacitor and deep trench capacitor for feature-rich and cost-effective mixed signal applications. Our goal is to continue to develop highly differentiated and cost-effective technology solutions to meet the increasing application specific needs of our foundry customers.”

About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip Semiconductor has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, a large portfolio of registered and pending patents, and extensive engineering and manufacturing process expertise.

CONTACTS:

In the United States:

Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com

In Korea:

Chankeun Park
Senior Manager, Public Relations
Tel.+82-2-6903-3195
chankeun.park@magnachip.com